Signal Latchup deals with a silicon-controlled rectifier (SCR). However, the behavior is different from standard latchup in that the current monitored is from the I/O signal pad. During Signal Latchup, the anode is connected to the signal pin, whereas during standard latchup the anode is connected to the power supply; therefore, an additional latchup effect is possible if current into the signal pin is monitored. The design of voltage tolerant electro static discharge (ESD) protection can lead to Signal Latchup effects.
The primary prior art ESD protection structure used for a voltage tolerant signal pin is made up of cascode NMOS transistors M1 and M2 from the signal pad 20 to node Vss, and a series of at least 2 pn diodes from the signal pad 20 to the power supply VDD, as shown in FIG. 1. Diodes D1, D2, D3, and D4 are shown in FIG. 1 as an example. The actual number of series diodes can vary depending on what the voltage tolerant requirements are for a given design. There can be as few as 2 diodes (D1 and D2) in the series. The circuit of FIG. 1 also includes resistors R1 and R2. The placement of diode D1 with respect to the cascode NMOS transistors M1 and M2 is critical to the ESD operation. The parasitic pnp built into diode D1 is being used to pump the local substrate in order to turn on the composite parasitic NPN formed between the drain of transistor M1 and the source of transistor M2. Note that this effective NPN triggers when the cascoded devices are integrated in layout.
Since there are a series of at least 2 diodes involved, node A in FIG. 1 is a high impedance node that forms the base of the parasitic pnp substrate pump. Unfortunately, this parasitic pnp substrate pump is also part of a parasitic SCR that exists between the Pad and node Vss as shown in FIG. 2. Transistors Q1 and Q2, and resistors Rwell and Rsub in FIG. 2 represent parasitic devices between pad 20 and node Vss in FIG. 1.
From the Signal Latchup point of view, if current is pulled out of a neighboring pin while there is sufficient voltage applied across the parasitic SCR, high impedance node A can easily be pulled down to a base-emitter voltage (Vbe) and trigger the parasitic SCR which clamps the pad to node Vss. This results in destructive signal pin current that would go undetected during normal latchup testing where only the current at node VDD is monitored.
Since the neighboring pin plays an important role during Signal Latchup, the distance between the neighboring cell and the parasitic SCR cell is critical.
In application systems where Signal Latchup is present, the holding current depends on the input current that an external driver can provide. Also, the input voltage in the application plays a role. If the input/output (I/O) cell changes the input voltage to be below the holding voltage of the parasitic SCR then the I/O pin will not sustain the Signal Latchup. In order to activate the parasitic SCR with anode connected to I/O, a current pulse is needed in the neighboring cell when the input is connected to a voltage higher than the holding voltage of the parasitic SCR (High level in digital signal).
If the I/O is directly connected to a power supply source then it could result in a destructive failure. On the other hand, if it is connected to a bus, the failure could result from unexpected behavior of the system due to bus contention. In the latter case it could cause damage to the other IC's sharing the same bus on the system board.
Failure Mode: Due to Signal Latchup, the SCR appears with the anode connected to the I/O instead of coming from a power supply. This behavior depends on the trigger current from an adjacent cell.
The primary ESD protection structure used for a voltage tolerant signal pin with series PN diodes from the signal pad to the power supply could play an important role due to the parasitic SCR. Therefore, the layout and/or dimensions of the ESD NMOS and diode circuit are directly related to the Signal Latchup performance.